Each student is required to design a single input single output forward converter (with clamping circuit) topology as per the below specification:
|
Parameters
|
Values
|
|
Vin (V)
|
150-200
|
|
Vout (V)
|
30
|
|
Iout (A)
|
1-5
|
|
Efficiency (%)
|
90-92 %
|
|
Vout (ripple) (%) (Peak-Peak)
|
1
|
|
Operating Ambient temperature
|
0°C to 40°C
|
|
Switching frequency
|
< 150kHz
|
Table 1 Forward Converter Design Specification
Project Tasks:
1- Design the converter: Do the steady state analysis of the forward converter.
2- Select power switches and diodes: For the power switch selection, you need to come up with the rated blocking voltage and rated Rms and peak current of the switch. Since the switching frequency is high, a Power MOSFET is preferred so that the switching losses are kept within limits. Here, the RDS(on) of the MOSFET becomes important since it will determine the conduction loss which is the major loss contribution of MOSFET.
For the diode selection, you need to calculate the rated blocking voltage and average forward current of the diode. In selecting the power switch and diode, always consider a safety margin of at least 1.5. Based on your semiconductor selection, calculate the loss components associated with each semiconductor device and check them with your efficiency condition.
3- Select output capacitors: The capacitor selection should be done based on output voltage ripple requirements. After you have determined the rated voltage (including some 1.5 safety margin) and required capacitance, choose the output capacitor. You should consider the ESR (Equivalent Series Resistance) of capacitors at the corresponding switching frequency. This series equivalent resistance times the ripple current passing through the capacitor causes an extra output voltage switching ripples and also leads to capacitor heat-up and life cycle decrease. You should choose a capacitor with a low ESR such that the output ripple requirement is satisfied at the switching frequency. Having the output capacitor rms currents and their ESRs, you can also calculate the power loss in output capacitors. This is important with respect to capacitor losses and temperature rise, and efficiency requirements. (Cout)
4- Design the transformer:
The Bmax for transformer is 0.2 T and Ku = 0.6. Design the transformer using cores given in Appendix D of Erickson's textbook. You can use β = 2.7 and Kfe = 24 W/Tβ cm3. You need to do detailed transformer design and show all the steps with all design parameters and values. You are allowed to select cores from any manufacturer.
5- Clamping Circuit : Design a clamping circuit to minimize voltage overshoot across the main switch. You may use passive or active clamping circuit. Give details of your design with component selected.
6- Efficiency calculation and power loss distribution: after going through steps 1-4, plot the actual power loss distribution of the converter. Calculate and plot light load and rated load efficiency.
7- Deriving converter transfer functions: To accomplish this, you need to derive the small-signal model. Several approaches are being mentioned in chapter 7 of the textbook. This includes but is not limited to the method of "Averaged Switch Network". By solving your small-signal model, derive the following transfer functions in an ideal case: (ignore Rds, VF,etc)
a. Control-to-output TF: Gvd (s)
b. Line-to-output TF: Gvg (s)
8- Controller design and implementation: Controllers should be designed to regulate the output voltage. The specification is to keep a voltage constant at the converter output (Vout), and the objective is to achieve the maximum bandwidth and minimum rise time with voltage overshoot/undershoot not to exceed 15% in response to a voltage reference step. Please note that controller needs to be designed using hand-analysis (without MATLAB or other tools). After you have designed your controllers, plot the magnitude and phase Bode diagrams of closed- loop loop gain T(s)for controller by hand and highlight the important points. Bode plots should then be plotted using MATLAB to confirm the accuracy of plots.
8- Simulate your design using PLECS: Simulate your design and demonstrate different characteristic at light load and rated load. This also includes power switch and output voltage and current.
9 Project Deliverables:
You are required to turn in a design report in PDF format alongwith PLECS file in a zipped on the due date uploaded to the course website on Wolfware classic.
To help in project grading, please name the files as pecified below
a) Report as unityid_Rep_Lastname_firstname.pdf;
b) PLECS file as unityid_Sim_Lastname_firstname.pdf
c) Zipped folder as (unityid_Proj_Lastname_firstname.pdf).
The report must contain the following:
a) Title page with project name, your names, date, and an academic integrity statement.
b) A single paragraph executive summary.
c) A compliance table summarizing the simulated nominal performance of your circuit versus the specifications. This table should list the design requirements and then list your achieved results. Any specifications not met should be highlighted in red text.
d) Technical discussion of your design, explaining
a. Design of the forward Converter.
b. Design of transformers
e) Design is an iterative process. You may have to design multiple times to meet the specifications. Please submit 2 designs :
a. Preliminary design
b. Final design
All datasheets need to be submitted as Appendix for final design only. For preliminary design, please submit the type number of component selected along with Digikey/Mouser link as part of appendix.
f) Conclusion with comments of what changes would enhance the performance of your design. If some performance values do not meet specification then add clear discussion in the report as to what aspects of your design are limiting the performance and the trade-offs you made.
g) Clear and legible plots & graphs for following :
a. Output voltage.
b. Magnified view of output voltage with ripple
c. Magnitude and phase plots (bode plots) for open loop (without controller) [Hand plotted & using Matlab]
d. Magnitude and phase plots with Controller [Hand plotted & using Matlab]
e. Schematics with component values. Component values can be shown in PLECS.
f. Pie chart with loss distribution
h) Cite references in your report if you use any ideas from other sources (IEEE Papers, conferences, etc.)
Academic Integrity: Please note that it is an individual project. The design and reports must represent student's own original work. Absolutely no sharing of schematics, designs, plots and write-ups will be accepted. Students in violation of this policy will be reported to the NCSU Office of Student Conduct, with repercussions including placement on academic probation and grade penalties including but not limited to receiving a zero on the design project. Please refer to the NCSU Academic Integrity Policy (see syllabus) as well as the office of student conduct for the NCSU policies.
Extra Credit:
1. Analog Implementation of Controller :
a. Implement the controller transfer function with R-L-C circuit.
b. Step-by-step explanation of components selection with bode plots
2. Implementation using Current Mode Control instead of Voltage Mode Control
Design Project:
In two-person teams, you are to design a CMOS Low-Power Operational Transconductance Amplifier in 90-nm CMOS which meets the specifications listed below
|
Parameter
|
Required Specification
|
|
Low Frequency Gain
|
95 dB (56 V/mV)
|
|
Unity-gain Bandwidth
|
500 kHz (must be single-pole response)
|
|
Phase margin
|
75 deg, for unity gain feedback, no external load
|
|
Settling time
(1% of final value)
|
<6 msec (0.1% settling to final value) with 3pF external cap load
|
|
Output Swing
|
1.4 V-pk-to-pk differential (ppd)
|
|
Input common-mode range
|
At least 0.7-V overlap with the output signals
|
|
CMRR
|
>70 dB
|
|
PSRR+
|
>90 dB
|
|
Supply Voltage
|
1.5 V
|
|
Power dissipation
|
Pdiss < 30 mW
|
|
Slew rate
|
>0.2 V/usec
|
|
Input-Referred Noise Voltage Floor
|
<70 nV/√Hz in white portion
(should be white around 10-100 kHz).
Also, you must report the 1/f corner frequency
|
You must use the transistors in the 90nm GPDK, 1.2-V transistors. Additionally, you must design the op-amp to achieve one of the three following specifications listed below. Each additional spec met adds three points to your project grade-maximum of 9 points, where only one additional spec is minimum requirement needed to get 100.
1. Rail-to-rail operation, achieving common-mode input range of 0 to 1.5 V.
2. Fully differential output with embedded common-mode feedback, CMFB phase margin >75 deg.
3. Output buffered, including an output buffer capable of driving a load of 100 ohm in parallel with 3 pF. You can double the total op-amp power consumption. Also, if you choose this option, you must simulate the total harmonic distortion of the op-amp when placed in a negative feedback configuration with feedback resistors of 390ohm, load resistances of 800ohm, with closed-loop gain of 1. THD should be 0.1% or less.
Your design will be evaluated against the required specifications and then additional requirement #1-#3. You should refer to some typical op-amp data sheets to get a feel for typical performance results and how data is reported (e.g., https://www.ti.com/lit/ds/symlink/tlv2763.pdf --this is an op-amp I used for evaluating feasibility of the specs). The design is to be completed using Cadence for all circuit simulation. Tutorials are provided on-line on how to set up and use these tools. You will be using the 90-nm GPDK design kit from Cadence. Your circuit design must meet the following requirements:
1. No external bias other than a single power supply and common mode input voltage is allowed. You must provide your own bias circuits for currents and voltages.
a. Ideal voltage and current sources are not allowed in your final circuit. Points will be deducted from your project grade if ideal sources are found in your netlist. Points will be deducted if voltage-mode biasing is found.
2. You must implement supply-independent biasing.
3. You must compensate all feedback networks. This applies to common-mode feedback as well as any internal amplifiers used (i.e., for active cascodes). All loops must have the 75-deg phase margin.
4. No resistors (or series resistor chains) larger than 50k are allowed, as they take too much area.
5. All NMOS transistor bodies must be connected to ground; PMOS transistor bodies should be connected to VDD.
6. Your design must use hierarchy (no flat netlists), with at least the following levels
- External testbench which only includes input AC and common-mode sources, power supply, ideal baluns, and the op-amp subcircuit.
- The primary OTA/op-amp
- Subcircuits for bias networks, additional amplifiers used for active cascade, common-mode feedback.
You are to turn in a design report in PDF format (~15 pages, including figures) on the due date uploaded to the course website (please upload separate copies of the report-one into each team member's moodle account). You must title your report as follows: Grp_X_Lastname1_Lastname.pdf, where X is the number of the group assigned to you, Lastname1 is student 1 last name, and Lastname2 is student 2 last name.
Academic Integrity: These designs and reports must represent your team's own original work. The actual CMOS amplifier designs must be unique. Absolutely no sharing of schematics, designs, plots, write-ups will be accepted. Absolutely no use of prior-year reports or prior-year designs. Students in violation of this policy will be reported to the NCSU Office of Student Conduct, with repercussions including placement on academic probation and grade penalties including but not limited to receiving a zero on the design project. Please refer to the NCSU Academic Integrity Policy (see syllabus) as well as the office of student conduct for the NCSU policies.
The report must contain the following:
1. Title page with project name, your names, date, and an academic integrity statement. In your project name, please include either "Fully-differential", "Rail-to-rail", or "Output-buffered" to designate the design option you selected.
2. A single paragraph executive summary (this is the most important part of any report...if I read nothing else but this section, convince me of the merit of your design).
3. A compliance table summarizing the simulated nominal performance of your circuit versus the specifications. This table should list the design requirements and then list your achieved results. Any specifications not met should be highlighted in red text.
4. Technical discussion of your design, explaining
a. high-level design of the OTA/op-amp and the architecture selected;
b. a discussion of the hand calculations used for designing the op-amp;
c. a discussion of any feedback loops used within your OTA and how they operate and how they were compensated;
d. a discussion of the supply-independent biasing circuit(s);
e. a discussion on the particular design option you selected and additional details of the design of this block;
f. a comparison of your hand calculation to the results achieved in simulation;
g. a section which summarizes the trade-offs you observed within the design project. Also, if particular performance values do not meet specification then add clear discussion in the report as to what aspects of your design are limiting the performance and the trade-offs you made. This last part is important, as it may become clear that you are unable to meet each and every spec.
5. Conclusion with comments of what changes would enhance the performance of your design.
6. Two sets of schematics (black on white background only, no screen shots, must be legible-Note, this is a place where easy-to-obtain points are deducted. Spend the time to make very clear schematics. Cadence allows you to do so if you save the images properly)
a. one set with design values clearly labeled and easily readable parameter values
b. the other set with DC voltages and operating points clearly readable
c. these schematics must be for the full design hierarchy
7. Cite references in your report if you use any ideas from other sources (journals, conferences, etc.) Any figure copied from any other document must be referenced. Screen shots from other journals or even my notes are not acceptable. You should draw your own schematics from scratch.
8. A set of simulation results (clear and easy to read-no screen shots):
a. Frequency response of the amplifier, indicating gain, bandwidth, and phase margin with no capacitive load (but including internal compensation).
b. Frequency response of any internal feedback loop, i.e., gain booster, indicating gain and phase margin. Every feedback loop must be simulated and compensated.
c. Step response of the amplifier when driving the external capacitive load, indicating settling time.
d. DC/AC sweeps indicating the input range.
e. DC/AC sweeps indicating the output range.
i. A simulation showing the input to output range overlap. For this simulation, you should add ideal 1:1 buffers using the vcvs component and then place the fully-differential op- amp into unity-gain feedback using resistive feedback.
f. Common-mode rejection ratio frequency response (using the ideal_balun in analogLib will be very helpful for the differential and common-mode simulations).
g. Power-supply rejection ratio frequency response (positive supply only)
h. Frequency response of the input equivalent noise voltage (from a NOISE analysis)
i. For Option 1: show the DC/AC sweeps (d) and indicate rail-to-rail operation clearly.
j. For Option 2: frequency response of the common-mode feedback loop, indicating gain and phase margin (refer to the feedback lecture on how to break a feedback loop in SPICE).
k. For Option 3: show a simulation illustrating output buffering capability, with the required loads, which still meets slew-rate and settling time requirements.
You will demonstrate the design to the TAs by taking them through the schematic and key simulation results. Details will be provided on the timing of this demonstration.
Attachment:- database.rar