Introduction to Computer Engineering Design Project: Design and Implementation of an Arithmetic Logic Unit on the DE0 Nano board
Topic: verilog
Honor Code Requirements -
Each student must complete this project and the associated report individually. Do not discuss any aspect of your solution or approach with anyone except for your instructor or a CEL GTA. Consider all information that you derive from your design process to be proprietary. Among other things, this includes the manner in which you implement your operations, and the number of chips that you use. Copying or using any other person's design is a violation of the Virginia Tech Honor Code, and will be prosecuted as such. You may discuss general features of Quartus and the DE0 Nano board. Direct all other questions to your GTA or to your instructor.
Objectives
- Design, simulate, and implement an Arithmetic Logic Unit from a specification.
- Write a project report describing the design process and its results.
Preparation -
You must have access to a computer that can run Quartus. You must have a DE0 Nano board.
Read this project specification in its entirety. Consult the appropriate sections of Chapter 3 and Chapter 8 of the textbook.
You should also consult the DE0 Nano board user's manual, particularly Chapter 3 and 6. This lab follows a simplified version of the steps described in Chapter 6 of the user's manual.
Project Description -
An arithmetic logic unit (ALU) is a combinational circuit that performs a variety of common arithmetic, logic, and shift operations. An ALU has a set of control inputs that determine which of the operations will be carried out on a set of operands. For this project, the ALU will take as input two 8-bit operands, A and B, and perform the operation on those operands specified by a 4-bit operation code (opcode). The ALU will generate the 8-bit result of the operation as well as four status bits. The set of operations that you are required to implement is specified in Table 1.
Requirements and constraints -
1. You are permitted to modify only the Verilog file your_ALU_mux.v, and the ROM contents file, rom.txt. You must not modify any other file or schematic in the project. Any additional modules that you might need to create to implement your design should be included in the your_ALU_mux.v file.
2. You are not permitted to modify the port declaration of the your_ALU_mux module.
3. You must implement your design using structural and dataflow Verilog constructs (gate primitives, assign statements with operators). You are not permitted to create any schematics or to use behavioral Verilog constructs (e.g., case statements, for loops). Note that if you use dataflow Verilog it will be more difficult to determine your gate count and propagation delay.
4. Your design must be completely combinational.
5. Your design must display the last four digits of your student ID number as shown in Table 3.
Circuit Validation -
This project does not require CEL validation. Instead, you will provide the source files that will allow the GTA to compile the same files that you used to implement your ALU on the DE0 Nano Board. Create an archive of your work by choosing Project > Archive Project after you complete the implementation. When you create the archive, it should appear in the same folder that was created when you opened the original archive. Upload the archive to Canvas. Make certain that you upload the completed archive that you created, and not the one that was provided to you.
Project Report -
After you have validated your logic circuit, prepare and submit a written lab report that presents a detailed discussion of the project. It should include the design approach you followed, the final design you implement, the design decisions that you made and the alternatives you considered, your simulation results, your observations, and your conclusions. Subdivide your report into logical sections and label them as appropriate. The last two pages of your report must be the validation sheet. Be sure to include all the required elements. Refer to the Assignment rubric to see how this project will be graded.
Attachment:- Assignment Files.rar