The basic functionality of a D flip-flop can be implemented by a JK flip flop simply by connecting the input signal D to the JK flip-flop's J input and the D to the K input.
Draw a timing waveform for the clock, input D, and outputs Qpos, Qneg, and Qms that illustrates the differences in input/output behavior of a positive edge-triggered D flip-flop, negative edge-triggered D flip-flop, and master/slave flip-flop (implemented from a JK master/slave flip-flop as described in the text). Include some transitions on D while the clock is asserted.