assume that an implicit rising clock is ANDed with every finite state machine (FSM) transition condition.
Draw a state diagram for an FSM (Moore machine) with no inputs and three outputs x, y, and z, where xyz should always exhibit the following sequence: 000, 001, 010, 100, repeat. Make 000 as the initial state. The output should change only on a rising clock edge. Also, add an input I that can stop the sequence when set to 0. When input I returns to 1, the sequence resumes from where it left off.