Determine the Uses of memory blocks.
Not as common a technique though something to consider. As Verilog has a very convenient syntax for declaring and loading memories, you can store your input data in a hex file and use $readmemh to read all the data in at once.
In your testbench:
module testbench;
...
reg [31:0] control[0:1023];
...
initial $readmemh ("control.hex", control);
...
endmodule
You could vary the filename using previous approaches. Control.hex file is just a file of hex values for the parameters. Fortunately, $readmemh allows embedded comments, so you can keep the file very readable:
A000 // Starting address to put boot code in
10 // Activate all ten input pulse sources
... etc...
Apparently, you are limitied to actual hex values with this approach. Note, of course, that you are free to mix and match all of these techniques!