Desing a logic Circuit that receives an array X(4 bits:X1,X2,X3, and X4) and makes it available as an output O(4 bits: O1,O2,O3, and O4) after one clock delay, subject to the control of input signals : "a" and "b". If a=b=0, then the data is NOT transferrer. If a= 0 and b=1, then the data is transferrer without modification. If a=1 and b= 0, the data is rotated, one place right(shift right). If a=1 and b=1, the data is rotated one places left( shift left).