Consider the NMOS inverter with depletion load in Figure 16.7(a). Let VDD = 1.8 V, and assume VTND = 0.3 V and VTNL = -0.6 V.
(a) Design the circuit such that the power dissipation is 80μW and the output voltage is vO = 0.06 V when vI is a logic 1.
(b) Using the results of part (a), determine the transition points for the driver and load transistors.
(c) If (W/L)D found in part (a) is doubled, what is the maximum power dissipation in the inverter and what is vO when vI is a logic 1?
