In this problem, you will explore the design of a 32-bit prefix adder.
(a) Sketch a schematic of your design.
(b) Design the 32-bit prefix adder in an HDL. Simulate and test your adder to prove that it functions correctly.
(c) What is the delay of your 32-bit prefix adder from part (a)? Assume that each two-input gate delay is 100 ps.
(d) Design a pipelined version of the 32-bit prefix adder. Sketch the schematic of your design. How fast can your pipelined prefix adder run? You may assume a sequencing overhead (tpcq + tsetup) of 80 ps. Make the design run as fast as possible.
(e) Design the pipelined 32-bit prefix adder in an HDL