Design and provide the logic circuit of a 4 bit counter usingthe same techniques used to design synchronous sequential machines.The counter has three inputs: EN (Enable), OD (Order), and ST(Step). The initial output of the FSM is 0000. When the EN signalis set to 1, the counter starts counting. When EN = 0 the countermaintains its current output. If OD = 0, the count is in ascending order and the resets to 0000 after 1111, and if OD = 1, the countis descending order, and the count moves to 1111 after 0000. The signal ST decides the step of the count. If ST = 1, the count is insteps of 1. If ST = 0, the count is in steps of 2.