Design an expandable 2-bit magnitude comparator


Problem 1: Design a 2-bit magnitude comparator as depicted below. Specifically, create a truth table and then obtain minimal Boolean equations in SOP form for each output of the comparator. You do not need to draw a schematic. Note that A[1] is the MSB of A[1:0].

1485_Magnitude comparator.png

Problem 2: Design an expandable 2-bit magnitude comparator which can be used as shown below. You do not need to draw a schematic. The equations do not need to be minimal but must be incorporate the equations you derived above. Note that A[3] is the MSB of A[3:0].

332_2-bit magnitude comparator.png

Problem 3: In the communications scheme below three data bits are transmitted along with a parity bit from the source to the destination. The data should have even parity. Design both the parity generator and parity checker functions. The parity checker should output a 1 if there is a parity error. Use the fewest gates possible. You may use inverters and 2-input AND, OR, XOR, XNOR gates.

1666_Communications scheme.png

Problem 4: Design a 16-to-1 mux using only 4-to-1 multiplexers.

Problem 5: Design a circuit to multiply two unsigned 2-bit numbers using only 2-input AND gates and single-bit half adders.

Problem 6: What function is performed by the following ALU circuit when {M,P} = {01}?

1702_ALU circuit.png

Problem 7: Analyze the following synchronous state machine to determine its functionality by obtaining the next-state equations, the PS/NS table, and the state diagram. Does the state machine have any illegal states? What is the name of the counting sequence?

2478_Synchronous state machine.png

Problem 8: Assuming all the flip flops in the circuit below are initialized to zeros, show the output sequence it generates.

1228_Flip flops.png

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Electrical Engineering: Design an expandable 2-bit magnitude comparator
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