Design a Verilog system that will accept a block of data words encoded as specified in Part 1; then check the parity for each data word and for the block. The system should output each of the 8-bit data words, issue a word error if the parity is incorrect for any word, and issue a block error if the block check word is in error. Below is part 1 with my answer: Part 1: Design a Verilog system that uses a block code for error management. The system should accept a 15-word block of 8-bit data words one word at a time, generate odd parity over the individual words, and even parity over the block, output each of the 15 9-bit data words, followed by the block check. My Answer: character.module assert_immediate(); reg clk, request; time current_time; initial begin clk = 0; grant = 0; request = 0; #4 request = 1; #4 grant = 1; #4 request = 0; #4 $finish; end always #1 clk = ~clk; //================================================= // Assertion used in always block //================================================= always @ (posedge clk) begin if (grant == 1) begin CHECK_REQ_WHEN_GNT : assert (grant && request) begin $display ("Seems to be working as expected"); end else begin current_time = $time; #1 $error("assert failed at time %0t", current_time); end end end endmodule