Question - Design a task or function that will check the parity of a word for odd parity. The input to the task/function is a 5-bit word called data_in. If the parity of input data_in is not odd increment an error count in your testbench. Parity is determined from the number of ones in a word. For example if data_in=5'b10101, data_in would have odd parity. If data_in=5'b01001, data_in would not have odd parity.
Requirements:
a. Implement in Verilog the task or function.
b. Call your task/function from a testbench and test it thoroughly.
c. Turn in your task/function and testbench code as well as a simulation waveform.