Design a sequential system that has a clock pulse input and produces a pulse that is coincident with every 25th clock pulse. (We do not care about initializing the system.) The only available components are
1. AND gates (any number of inputs)
2. Inverters (NOT gates)
3. Two base 16-counters (as described below)
The counter is trailing-edge triggered. It has four outputs- D (high-order bit), C , B, and A. It has a clock input and an active low static Clear input. There is also an active low static Load input, along with data input lines, IND , INC , INB, and INA. (Assume that Clear and Load are never both 0 at the same time. When either is 0, it overrides the clock.)
a. Design a system using these components that uses the Clear input, but not the Load input.
b. Design a system using these components that uses the Load input, but not the Clear input. 6. Des