Lab Synchronous Counter Design
This is a simulation only lab:
Design a synchronous counter that will count the following sequence. 0, 1, 4, 5, 8, 9, 12, 13 and then recycle. Implement your circuit using negative edge-triggered J-K Flip Flops (74LS76). The clock will be a 5V, 1Hz pulse signal.
You will submit your design process in a neat and orderly (digital) manner. Construct and simulate the entire circuit in Multisim. Use the 4-channel oscilloscope to verify the count sequence. Beneath the o-scope use the waveforms to list the count sequence.
This lab may be completed at your convenience. You may work on this lab in NE 2380 during your scheduled lab time if you wish or in any of the computer labs on the engineering campus at your convenience.
REQUIRED SUBMITTAL: You will NOT turn in this handout!
You will do a full formal lab report including the following sections:
OBJECTIVE (Sentence / Paragraph format. Be thorough!)
PROCEDURE (Numbered steps)
DATA - Every step of the design process (there are 5, plus the implementation). Use Multisim to implement and simulate the counter design. Verify its function by showing the oscilloscope output of the count sequence.
DISCUSSION (Sentence / Paragraph Format)
CONCLUSION (Sentence / Paragraph Format)