Design a logic circuit for the binary multiplier control unit whose ASM diagram was designed in Example 8.20 using a minimum number of 1K flip-flops.
Example 8.20:
We wish to design the control unit for a binary multiplier that will compute the 8-bit product of two 4-bit unsigned binary numbers using a series of add and shift operations. The multiplier begins when pulsed by a Reset signal and halts with the product on its outputs. A Halt signal indicates the end of the operation.