1. Design a circuit that has 4 inputs, WXYZ, and two outputs, f and g, where W is the most and Z is the least significant bit. The output f is asserted whenever the two-bit number WX is greater than the two-bit number YZ. The output g is asserted whenever the 4-bit number represented by WXYZ, is evenly divisible by 4. Design this circuit using gates. Sketch the SOP realization using NANDs only. Sketch the POS realization using NORs only. (You should treat each output separately and determine the truth table for each.)
(MSB) W
X f
Y g
(LSB) Z
2. Repeat Problem 1 using 8-to-1 MUXes and a minimal amount of gate logic. Sketch the resulting circuit indicating how the MUXes are to be connected to generate the outputs, f and g.
3. Repeat Problem 1 using a 4-to-16 decoder and a minimal amount of gate logic.