It is an rchiticture class: Memory Hierarchy.
The question is: Assuming the address is 32bits
a) What is the size of a process page table (in Bytes) for a 16KB page size?
b) The above page table is itself paged and the processor contains a TLB. Describe the translation process for the first instruction fetch in a program. Define any variables you may need.
c) Draw a complete block diagram for the memory hierarchy in this case, using a virtually-indexed, physically tagged L1 cache. Assume a fully associative TLB and the cache from Pr. 1a). Show the size of all fields (in bits).