Assume that there is an SPI-compatible peripheral output device that has the following characteristics:
• A CLK input pin that is used as the data-shifting clock signal. This signal is idle low and data is shifted in on the rising edge.
• An SI pin to shift in data on the falling edge of the CLK input.
• A pin, which enables the chip to shift in data when it is low.
• A highest data-shifting rate of 1 MHz.
• Most significant bit shifted in first.
• All interrupts disabled.
• The SPI0 module stopped in wait mode and freeze mode.
• The pin used as a general I/O pin.
Describe how to connect the SPI0 pins for the HCS12 and this peripheral device and write an instruction sequence to configure the SPI subsystem properly for data transfer. Assume that the E-clock frequency is 24 MHz.