FINAL PROJECT -
Topic: Computer Engineering Digital logic using Veirlog
Objectives - The main objective of the final project is to allow you to put together all of the class material that you have learned so far in order to program the Altera DE2 board to carry out an independent activity. You will have the opportunity to design a circuit to realize one digital system that accepts input from switches and outputs to LEDs and 7-segment displays.
Project Selection - A project is suggested below. If you do not like the suggested project, you have the option of specifying your own project. If there is something that you have always wanted to do, now is your chance. Your project MUST be of appropriate complexity as determined by the lab TAs. The minimum requirements are that your project MUST: 1) include a finite state machine, 2) include a register file, 3) include some combinational logic circuits, and 4) be demonstrated on the Altera DE2-115 board provided in the lab.
Project Description: Handheld Calculator
In this project, we would like to design a digital system that turns the Altera DE2-115 board into a simple handheld calculator. The schematic of the system is presented in the following figure:
The system contains four registers R0 - R3, each of which stores a 5-bit unsigned integer. Several basic operations acting on the registers should be implemented. A 3-bit input OP specifies an operation to be performed and a 2-bit input k specifies a parameter with a value between 0 and 3. The inputs OP and k should first be set up when the signal PERFORM is 0. Then the signal PERFORM can be set to 1, and the specified operation will be performed. After that, the signal PERFORM can be reset to 0 to prepare for another operation. The Reset signal will set all registers to 0 and the control FSM to its initial state. Switches/buttons can be used to specify the inputs. The values stored in all four registers should be displayed in decimal by 7-segment displays.
The required basic operations are listed in the table below.
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OP
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Operation
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000
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R0 ← 0, R1 ← 1, R2 ← 2, R3 ← 3
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001
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R0 ← k
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010
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R0 ← Rk
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011
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Rk ← R0
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100
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R0 ← R0 + Rk
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101
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R0 ← R0 - Rk
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10
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R0 ← R0 x Rk
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111
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R0 ← 2Rk
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The system should contain a datapath circuit and a control circuit. The datapath should contain the four 5-bit registers organized as a register file. The register file should have one input port and one output port with the following input and output signals:
R0 - R3: Contents of registers 0 through 3 (displayed via 7-segment displays).
WA: Write register address
LD_DATA: Input data to be written to the register identified by WA
WR: Write enable
RA: Read register address
DATA: Content of the register identified by RA
Besides, the datapath should contain an arithmetic unit (some combinational logic circuits implementing some arithmetic functions) to support the operations. The control circuit should be a finite state machine which produces the control signals to direct the datapath to execute the operations step-by-step.
Each of the below steps must be in its own design file. Demonstrate each step individually to receive credit.
a. Design and demonstrate that the 5-bit wide 4-register file works by writing and reading from the register file. You should use the 7-segment displays to show the contents of the register file.
b. Design and demonstrate the arithmetic unit to support the operations.
c. Design and demonstrate the finite state machine for the control circuit. Show that it produces the correct output.
d. Put together all the individual components in Parts a, b, c, and demonstrate the complete handheld calculator. You must design at least two test plans. Each test plan should demonstrate all 8 operations.
e. Final Report (see file "CPRE281 FinalProject_WhatToSubmit.pdf").
Attachment:- Final Project Assignment Files.rar