(Counter/Register Applications) Consider the design of a bit-serial adder. This circuit uses a single full adder to add tow binary numbers presented in serial fashion, 1 bit at a time.
(a) Draw the schematic for a 4-bit version of this circuit. Two 4-bit shift registers are loaded with the data to be added in parallel. These are shifted out a bit at a time, stating with the lowest-order bit, into the A and B inputs of the full adder. The partial sum is shifted into a third register. How should the carry out be handled between subsequent bits?
(b) Define your control signals for the bit-serial adder subsystem. Draw a timing diagram that illustrates the sequencing of these signals to implement the 4-bit addition. What happens on reset?