Consider a 256kb 4-shy-way set associative cache using


Consider a 256KB, 4-­-way set associative cache using 64-­-byte lines and LRU replacement using counters). The cache uses MESI cache coherence protocol. Addresses are 32-­-bits. Express your answers in bytes or KB kilobytes).

a)What is the total size of the cache including both data and tag arrays (tag, LRU, MESI bits)?

b)To reduce thrashing you consider making the cache 8-­-way set associative while keeping the overall size of the data portion of the cache the same. How much more (or less) space is now needed?
Show your work. What other resources that would require a larger die are necessary?

c)As an alternative, you consider adding a 16 entry, fully associative victim cache using LRU replacement. How much more space is required by the victim cache (including both data and tag arrays)? What other resources are necessary?

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Electrical Engineering: Consider a 256kb 4-shy-way set associative cache using
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