Computer Organisation Coursework Assignment
Coursework Aim - This exercise will allow you to writing programs in the language of the computer and understand how pipelining improves efficiency by executing multiple instructions simultaneously.
Module learning outcomes assessed in this piece of coursework - This assessment is designed to assess your ability in the following module learning outcomes:
- Describe and differentiate between the essential features and operations of modern computer architectures
Coursework brief - The assignment consists of two problems that you need to solve during the module workshops. Both have equal weights. (The problems are given at the end of this Assessment Form). You should submit an individual written report that provides the answers and a related discussion for each problem.
Assessment Problems -
Problem 1 - The C-code shown below will loop through an array of marks (integer values between 0 and 100) and calculate a histogram of these marks.
int A, B, C, D, F; // declare grade counters
inti; // declare loop counter
int N; // Number of scores to analyse
A=0; B=0; C=0; D=0; F=0; // initialize grade counters
// Read in test scores into gradesarray?
// N will be equal to the number of grades
// assume N = 50
for (i=0; i
if(scores[i] >= 90)
A = A + 1;
else if(scores[i] >= 80)
B = B + 1;
else if(scores[i] >= 70)
C = C + 1;
else if(scores[i] >= 60)
D = D + 1;
else
F = F + 1;
}
Q1. Write the equivalent MIPS assembly code for the C-code shown above.
You should assume the following:
- The number of scores, N, to be analysed is 50.
- The address of the first element in the marks array is contained in $s0.
Additionally, to make it easier for you to keep track of register assignments, you may use register names that have the same name as the variable names used in the code above. For example, to initialize the register that holds the A counter, you might write:
add $A, $0, $0
If you do choose to use actual MIPS register names, you should write your code out as follows i.e. with appropriate comments:
add $t0, $0, $0 # $t0 maps to variable A; we need to initialize it to 0
Problem 2 - This problem consists of two questions Q1 and Q2 which consider the basic MIPS 5-stage pipeline (F, D, EX, M, WB). You should assume that there is full forwarding.
Q1. Show how the instructions below proceed through the pipeline and indicate if any stall cycles are needed. You should assume the beq instruction is taken. Use the following chart.
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lw $1, 0($2)
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add $2, $2, $2
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sub $2, $2, $1
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beq, $2, $2, X
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lw $1, 4($2)
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X: add $2, $2, $1
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Q2. Assume the following sequence of instructions is executed in a traditional 5-stage pipeline. Does the lw / add instruction combination represent a data hazard? If so, why? If not, why not?
lw $5, 4($6)
sub $6, $5, $10
add $7, $6, $5