(Hardware Description Languages) Write a Verilog module that describes the circuit of Exercise 3.24.
Exercise 3.24
(Design Problem) Consider a combinational logic subsystem that determines if a 4-bit binary quantity A,B,C,D in the range of 0000 (0) through 1011 (11 in base 10) is divisible by the decimal numbers two, three, or six. That is, the function is true if the input can be divided by the indicated amount with no remain-der (e.g., By2(0110), By3(0110), and By6(0110) are all true). Assume that the binary patterns 1100 (12) through 1111 (15) are "don't cares."
(a) Draw the truth tables for By2(A,B,C,D), By3(A,B,C,D), By6(A,B,C,D).
(b) Minimize the functions using 4-variable K-maps to derive minimized sum-of-products forms.
(c) Can you further simplify the result by using a multilevel-logic implementation? If so, how?