The following code segment, consisting of six instructions, is to be executed 64 times for the evaluation of vector arithmetic expression: D(I) = A(I) + B(I) X C(I) for 0 I 63 Load R1,B(I) Load R2, C(I) Multiply R1, R2 Load R3,A(I) Add R3, R1 Store D(I), R3 /R1 Memory( + I)/ /R2 Memory( + I)/ /R1 (R1) X (R2)/ /R3 Memory( + I)/ /R3 (R3) + (R1)/ /Memory( + I) (R3)/ Where R1, R2, R3 are CPU registers, (R1) is the content of or R1, and , , , , are the starting memory addresses of arrays B(I), C(I), A(I) and D(I) respectively. Assume four cycles for each Load or Store, two cycles for the Add, and eight cycles for the Multiply on either a uniprocessor or a single processing element (PE) in an SIMD machine. a) Calculate the total number of CPU cycles needed to execute the above code segment repeatedly 64 times on an SISD uniprocessor computer sequentially, ignoring all other delays. b) Consider the use of an SIMD computer with 64 PEs to execute the above vector operations in six synchronized vector instructions over 64-component vector data. Calculate the total execution time in cycles on the SIMD machine, ignoring instruction broadcast and other delays. c) If both the SISD and SIMD machines run at the same clock speed, what is the speedup gain of using the SIMD computer over the SISD computer?