Question:
Cache: Expected access time, Address reference format
1. Answer the following questions related to reference addresses:
a. Given a 64-byte cache block, a 4 KB direct-mapped cache (assume byte-addressable), and a 32 bit address reference, which bits would be used for tag, index, and offset?
b. Given a 64-byte cache block, a 32 KB direct-mapped cache (assume byte-addressable) and a 32 bit address reference, which bits would be used for tag, index, and offset?
c. Given a 64-byte cache block, a 512 KB fully associative cache (assume byte-addressable), and a 32 bit address reference, which bits would be used for tag, index, and offset?
d. Given a 128-byte cache block a 2 MB 8-way set associative cache (assume byte-addressable, and a 64 bit address reference, which bits would be used for tag, index, and offset (note that `way' denotes the number of blocks)?
2. Answer the following questions:
a. What is the expected access time for the following cache configuration: Primary Cache: access time, 1 cycle; hit ratio, 80% Secondary Cache: access time, 10 cycles; hit ratio, 96% Memory: access time, 100 cycles.
b. Additional Primary or Secondary cache could be added at same cost. If additional primary cache results in a 92% hit rate and additional secondary cache results in 97% hit rate, which would be the better addition?