Assume that your application has 600 data reads for each 4000 instructions. For the same number of instruction the application has 400 data writes. The cache used has an instruction miss rate of 0.6% and a data cache miss rate of 6%.
Each block data size has 32 bytes and the cache is direct mapped and holds 32 kbytes of data.
If the cache is write back, and that 40% of the replaced data cache blocks are dirty, if the needed CPI is 3, what is the minimal read and write bandwidth needed?