A computer system has a four-stage pipeline consisting of an instruction fetch unit (F), an instruction decode unit (D), an instruction execution unit (E), and a write unit (W). Compute the speed-up time P(4), throughput U(4), and the efficiency z(4) of the pipeline in executing a code segment consisting of 20 instructions, given that branch instructions occur as follows: I3, I9, I10, I15, I20.
Assume that when a branch instruction is fetched, the pipeline stalls until the next instruction to fetch is known. Determine the time required to execute those same 20 instructions using two-way interleaved memory if the functions performed by the F, E, and W units require the use of the memory. What is the average number of cycles per instruction in both cases?