Assume that the initial value of R3 is R2 + 496. Use the classic five-stage RISC integer pipeline and assume all memory accesses take 1 clock cycle.
(a) Show the timing of this instruction sequence by filling the above table with normal forwarding hardware but assuming a register read and write in same clock cycle 'forwards' through the register. Assume that branch is handled at Decode Stage by introducing a separate Adder for effective address calculation. Also assume that branch is handled by flushing the pipeline.