Architecture of tms320c24 processor


1) Determine the DFT of the sequence x (n) = { 1, 2, 3, 4, 4, 3, 2, 1} using the DIT algorithm.

2) Given the sequences x(n) = { 2,1,1,2} and h(n)= { 1,-1,-1,1}.

Calculate the circular convolution for N=4. Make use of DIT-FFT algorithm.

3) Develop a chebyshev IIR digital filter utilizing the bilinear transformation

0.8 ≤ | H(e jω) | ≤ 1 0 ≤ ω ≤ 0.2π

          | H(e jω) | ≤ 0.2 0.6π ≤ ω ≤ π

4) Find system function H(z) of the lowest order Butterworth filter considering the following given specification.

a) 3 dB ripple in pass band 0 ≤ ω ≤ 0.2π

b) 25dB attenuation in stop band 0.45 π ≤ ω ≤ π

5) a) By using the rectangular window technique develop a lowpass filter with pass band gain of unity, cut off frequency of 1000Hz and working at the sampling frequency of 5kHz. The length of the impulse response must be 7.

b) Develop the FIR filter approximating the ideal frequency response

Hd(e -jω ) = e-jαω for | ω| ≤ π/6

                   = 0 for π/6 < |ω| ≤ π

 Compute the filter coefficients for N= 9.

6) Develop an ideal low pass filter having a frequency response

 Hd(e jω ) = 1 - π/2 ≤ ω ≤ π/2

                  = 0 π/2 < ω ≤ π

Determine the values of h(n) for N=1. Also compute H(z) and plot the magnitude response.

7) a) Determine the steady state noise power in the output because of the input quantization for a first order discrete time system having difference equation. y(n) = a y(n-1) + x(n)

b) Explain what is meant by the truncation? Describe the error which arises because of truncation in the floating point numbers.

8) Determine the effect of quantization on the pole locations of the given second order IIR system, when it is realized in direct form –I and in the cascade form. Suppose a word length of 4 bits through truncation.

9) Discuss the architecture of TMS320C24 processor.

10) Write down the MATLAB program for controlling the speed of PMDC motor.

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Electrical Engineering: Architecture of tms320c24 processor
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