SP1. An h-bit magnitude comparator is a circuit with two h-bit unsigned binary inputs, x and y, and two binary outputs designating the conditions x < y and x > y. Assume that x = y output is not provided.
a. Present the design of a 4-bit magnitude comparator (give the design equations).
b. Show how five 4-bit comparators can be cascaded to compare two 16-bit numbers (use block diagrams).
c. Show how a three-level tree of 4-bit comparators can be used to compare two 28-bit numbers. Try to use as few 4-bit comparator blocks as possible.