A CMOS circuit includes a pairof N-doped regions, separated by a P-doped channel, as well asP-doped regions, separated by an N-doped channel. Although this forms PNP and NPN transistors, the bias of the regions isdesigned so the junctions are reverse biased and the electric fieldeffects on the channel are supposed to control the MOS-FETtransistors operations. There is a failure mode of a CMOScircuit where the bias conditions are violated. What is thefailure mode, what causes it, what effects does it cause, and what is the simplest recovery mechanism.