1. Use iterative consensus to find a minimal SOP expression for:
F(W,X,Y)) = SWXY (0,3,6,7) + D(1,5)
2. Use K-map reverse engineering to evaluate if the following SOP functions are minimized? If not, find the minimal SOP expression.
(a) F(A,B,C,D) = A'C'D' + A'C + AB'C' + ACD'
(b) F(W,X,Y,Z) = XY' + WX'Y' + W'XYZ + W'X'YZ'
3. Are there any static-1 hazards in the following circuits? If so, how would you fix them? Write the expression after fixing it.
(a) F(A,B,C,D) = BC + B'C'D' + AC'D
4. Are there any static-0 hazards in the following circuits? If so, how would you fix them? Draw the fixed circuit.
(a) F(W,X,Y,Z) = (W+X+Z')(Z+Y)(Y'+X')
5. Half Adder:
(a) Construct the truth table of a half adder.
(b) Draw the circuit of the half adder.
(c) State the number of gate delays before the output is stable in the above circuit.
6. Full Adder:
(a) Construct the truth table of a 1-bit full adder.
(b) Using the block diagram of a 1-bit full adder, construct a 5-bit ripple carry adder
(d) State the number of gate delays before the output is stable in the above circuit.
7. Decoder:
(a) Show the truth table of a 3-input-8-output binary decoder (without enable logic).
(b) Construct a 3-input-8-output binary decoder using NOT, AND and OR gates (without enable logic)
(c) Using the above decoder, design the following logic function. Add the required gates and re-draw the decoder.
F(a,b,c) = Sabc (1,0,3,6,7)