A modulo 8 counter cycles through the states Q0Q1Q2Q3 = 1000,1100, 0100, 0110, 0010, 0011, 0001, 1001. The counter has eightoutputs: Z0 = 1 when the counter is in state 1000 and the CLK is 0and Z0 = 0 otherwise; Z1 = 1 when the counter is in state 1100 andthe CLK is 0 and Z1 = 0 otherwise, ...; Z7 =1 when the counter isin state 1001 and the CLK is 0 and Z7 = 0 otherwise. The counterhas an asynchronous, active-low reset input ClrN.
(a) Derive minumum equations for the counter outputs.
(b) Assume the counter is implemented using D flip-flops, FindMinimum input equations for the flip flops
(c) Assume the counter is implemented using D-CE flip flops,Find Minimum input equations for the flip flops
(d) Write a VHDL behavioral description of the counter. Assumethe flip-flops are positive edge triggered.
(e) Write a VHDL dataflow description of the counter using theequations from part (b). SImulate the counter for a cycle to verifyyour code.
(f) Write a VHDL dataflow description of the counter using theequations from part (c). SImulate and verify your code