--%>
Assignment Help - homework help

Explain VeriSoft

VeriSoft (Godefroid, 2005) is a model checker for C and C++; other languages can be used, but components in other languages are treated as black boxes. VeriSoft has been used to find defects in very large telecommunications programs (Chandra, Godefroid, and Palm 2002). It is available for download at the VeriSoft website. This package includes a version of VeriSoft for analyzing multiprocess C or C++ programs whose processes communicate via a predefined set of types of communication objects. It is a “stateless” model checker, in that visited states are not saved. It uses clever partial-order reduction search algorithms utilizing program analysis to avoid revisiting states, and guarantees complete coverage of the state space to some depth, while preserving correctness properties. Verisoft can search for four basic types of errors:

  • Deadlocks.
  • Divergences. A divergence occurs when a process does not attempt to communicate with the rest of the system for more than a given (user-specified) amount of time.
  • Livelocks. A livelock occurs when a process is blocked during a sequence of more than a given (user-specified) number of successive states in the state space.
  • Violations of state assertions, the assertions having been stated using a special operation VS_assert(boolean_expr).

To represent non-determinism in the model or environment, VeriSoft provides a special operation VS_toss to express non-deterministic choice, which is like Verify.random in Java PathFinder.

   Related Questions in Programming Languages

  • Q : What is Class Selector in the CSS

    Explain what is meant by the Class Selector in the CSS?

    		•
  • Q : Explain Operator Explain Operator with

    Explain Operator with their types and examples?

    		•
  • Q : Identify Customers in SQL The company

    The company wish to provide an incentive of free shipping to such customers who have not returned for 2 months. Build a procedure named PROMO_SHIP_SP which determines these customers are and then updates the BB_PROMOLIST table accordingly. The procedure employs the be

    		•
  • Q : What is Leverage Model-Based Design

    Leverage Model-Based Design: Model-based design provides useful hints of how a large system can be reduced so that its state space becomes searchable. If not inherently visible in the design (for example, by means of using a “State” design

    		•
  • Q : Rings present in CPU What do you mean

    What do you mean by rings present in CPU?

    		•
  • Q : Explain Aggregation Aggregation : It is

    Aggregation: It is a relationship in which an object has one or more other subordinate objects as portion of its state. The subordinate objects usually have no self-governing existence separate from their containing object. Whenever the containing obj

    		•
  • Q : What is a Micro-chip Micro-chip : It is

    Micro-chip: It is a small electronic device employed to build computers and other electronic equipment. The chips are generally employed to supply the memory and processing components of the computer.

    		•
  • Q : State the term VHDL or Verilog State

    State the term VHDL or Verilog? Answer: VHDL is extremely high speep integrated chips hardware descripted language as well as verilog is use to verify logic.

    		•
  • Q : Explain Polling Polling : It is the

    Polling: It is the process of repeatedly testing until a situation becomes true. Polling can be incompetent when the time between tests is little compared with the time it will take for the condition to become true or right. A polling thread must slee

    		•
  • Q : UK assignment & homework help Need UK

    Need UK Assignment Help, UK Homework Help. Get it now! HwA provides email based and live UK assignment help and UK homework help in a variety of subjects to the students based out

    		•