Q1. What do you mean by cache coherence? How can the problem are solved with a snoopy cache controller?
Q2. Illustrate the pipeline conflicts? How are they handled?
Q3. Describe the RS 232-C standard. State the merits of USB (Universal Serial Bus) over RS 232-C bus.
Q4. Show the layout of a cache for a CPU which can address 1M×16 of memory. The cache holds 8K×16 of data and has given mapping strategies. Find out the number of bits per location and the total number of locations.
a) Fully associative.
b) Directed mapped.
c) Four way set-associative.
Q5. With a neat block diagram, describe the working principle of the micro-sequencer. State the design methods and their limitations.