Describing booth multiplication algorithm-braun multiplier


1) Describe the major steps involved in the typical n-well CMOS process with suitable diagrams.

2)(i) Write a detailed notes on BiCMOS technology.

(ii) Compare n-well process and twin – tub process.

3) Write down the three regions of operation of nMOS transistors.  Explain the behaviour of the nMOS transistor in the three regions.          

4)(i) Write brief notes on Lambda based design rules.

(ii) What is meant by Latch-up problem?  Explain how to prevent latch up in CMOS?

5) Describe the various kinds of scaling used in MOS device.

6) Describe the circuits of: (i) Bit serial adder

(ii) Single-bit adder.

7)(i) Describe the structure of a Braun Multiplier.

(ii) Describe the Booth Multiplication algorithm with suitable example.

8)(i) Describe the structure of a PLA.

(ii) Write brief notes on memory design.

9) Describe the various data types used in VHDL.

10) Write down a VHDL program for a 4 bit adder by using:

(i) Behavioral Modeling

(ii) Structural Modeling.

Request for Solution File

Ask an Expert for Answer!!
Electrical Engineering: Describing booth multiplication algorithm-braun multiplier
Reference No:- TGS013322

Expected delivery within 24 Hours