Concept of TTL NAND Gate and its Circuit Analysis

TTL NAND Gate Circuit Structure:

The circuit structure is similar to the TTL inverter circuit apart from the multiple emitter input transistor. This is employed to implement a diode switching structure in active transistor form employing parallel junction diffusions for numerous emitters.

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Figure: Multiple Input Emitter Structure of TTL

When any input is low, the respective base-emitter junction becomes forward-biased and the transistor conducts. The other features of circuit and its transfer characteristic are similar to those of inverter circuit.

Logical Operation:

The table of conduction states can be drawn up exhibiting the state of each and every transistor in the circuit for all possible input conditions as prior to confirm the logic function performed. The direction of conduction of T1 can be in reverse or forward mode therefore this must also be noted in the table. This can be seen from the table that the output goes LO only whenever both inputs are HI that verifies the NAND function.

IN1      IN2      T1        T2        T3        T4      D      OUTPUT

LO         LO     ONfor     OFF      OFF      ON      ON         HI

LO         HI      ONfor     OFF      OFF      ON      ON         HI

HI          LO     ONfor     OFF      OFF      ON      ON         HI

HI          HI      ONrev     ON       ON      OFF     OFF        LO

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Figure: Circuit Diagram of a Standard 2-input TTL NAND Gate

Circuit Analysis:

It is of interest to observe the conditions for various logic states of NAND Gate circuit, specifically with regard to estimating the power consumption in each and every state. This can be initially done by establishing the voltages at each nodes of N1 – N7 in the circuit and then finding the net current drawn from the power supply.

a) At Least One Input LO – Output HI:

To help in the analysis, the NAND Gate circuit can be re-drawn with the transistors that are non-conducting or OFF eliminated from the circuit as shown in figure below. Then the potentials, relative to ground, can be find out for each of nodes in turn. Beneath this condition, T1 is ON in forward mode, T2 is OFF, T3 is OFF, whereas T4 is ON at the point of cut-in and thus T2 and T3 have been eliminated from the circuit.

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Figure: NAND Gate Circuit Redrawn with at least One Input LO

A) T1 ON in forward mode is operating in saturation as there is just a leakage current from T2 accessible as collector current, that is, T1 operates with a big base current and negligible collector current where IC MAX = 0. The input logic LO voltage is in use as 0.1V and then:

Node N1: VN1 = Vi + VBE1SAT = 0.1 + 0.8 = 0.9V

B) By T1 operating in saturation, its collector-emitter voltage is VCE SAT = 0.1V and hence:

Node N2: VN2 = Vi + VCE1SAT = 0.1 + 0.1 = 0.2V

C) With T4 operating at point of cut-in its base current and therefore its collector current can be taken as zero. This signifies that there is no voltage drop across either resistor R1 or R3 and hence the potential at both sides of such resistors is equivalent to the supply voltage VCC giving:

Node N3, Node N5: VN3 = VN5 = VCC = 5V

D) Node N4 is pulled low by resistor R2 that has no current flowing via it and hence:

Node N4: VN4 = 0V

E) At last, with T4 operating at the point of cut-in:

Node N6: VN6 = VN3 – VBE4CUT-IN = 5 – 0.6 = 4.4V

And with the diode at cut-in as well:

Node N7: VN7 = VN6 – VDCUT-IN = 4.4 – 0.4 = 4.0V

The current drawn from supply can then be obtained as:

IB = (VCC – VN1)/RB = (5 – 0.9)/4 KΩ = 1.025mA

With I1 and I3 = 0; as negligible current flows into the collector or base of T4 while at the point of cut-in.

Power consumption of the gate with output in the logic Hi state can then be received as:

POH = VCC x IB = 5V x 1.025mA = 5.125mW

Both Inputs HI – Output LO:

Under this case T1 is ON in reverse mode, T2 is ON, T3 is ON and T4 is OFF. Figure below shows the NAND gate circuit redrawn with T4 eliminated. Potentials should be determined in a different order this time.

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Figure: NAND Gate Circuit Redrawn with Both Inputs HI

With T3 ON and operating in saturation:

Node N4: VN4 = VBE3SAT = 0.8V

i) With T2 too ON and in saturation:

Node N2: VN2 = VN4 + VBE2SAT = 0.8 + 0.8 = 1.6V

ii) As T1 is ON in reverse mode, the base-collector voltage in this mode can be taken as similar as the base-emitter voltage of a transistor operating in forward active mode and hence:

Node N1: VN1 = VN2 + VBC1ONREV = 1.6 + 0.7 = 2.3V

iii) With T2 operating in the saturation, its collector emitter voltage will be VCE SAT = 0.1V and hence:

Node N3: VN3 = VN4 + VCE2SAT = 0.8 + 0.1 = 0.9 V

iv) With T4 OFF no current will flow via resistor R3 and as a result Node N5 will be pulled up to the supply rail voltage:

Node N5: VN5 = VCC = 5V

v) With T3 ON and in the saturation, its collector-base voltage will be at a saturation value and hence the output voltage at Node N7 is just:

Node N7: VN7 = VCE3SAT = 0.1V
 
vi) With T4 and diode non-conducting, the potential at Node N6 is rather ill-defined and depends on the resistances of the non-conducting junctions of such devices however will lie somewhere among that of Nodes N3 and N7, that is, between 0.1 and 0.9V. Though, this voltage is not important.

Current drawn from the supply, this time is given by the sum of IB and I1 including I3 = 0:

Then,

IB = (VCC – VN1)/RB = (5 – 2.3V)/4 KΩ = 0.675mA
 
And,

I1 = (VCC – VN3)/R1 = (5 – 0.9V)/1.6 KΩ = 2.56 mA

The power consumption whenever the output is LO is then as follows:

POL = VCC x (IB + I1) = 5 x (0.675 + 2.56) = 16.175 mW

When the NAND gate is supposed to spend half of its time in each and every logic state then the average power consumption can be stated as:

PAVE = (POH + POL)/2 = (5.125 + 16.175)/2 = 10.56 mW

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