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## Concept of TTL NAND Gate and its Circuit Analysis

TTL NAND Gate Circuit Structure:The circuit structure is similar to the TTL inverter circuit apart from the multiple emitter input transistor. This is employed to implement a diode switching structure in active transistor form employing parallel junction diffusions for numerous emitters.

Figure: Multiple Input Emitter Structure of TTLWhen any input is low, the respective base-emitter junction becomes forward-biased and the transistor conducts. The other features of circuit and its transfer characteristic are similar to those of inverter circuit.

Logical Operation:The table of conduction states can be drawn up exhibiting the state of each and every transistor in the circuit for all possible input conditions as prior to confirm the logic function performed. The direction of conduction of T

_{1}can be in reverse or forward mode therefore this must also be noted in the table. This can be seen from the table that the output goes LO only whenever both inputs are HI that verifies the NAND function.IN1 IN2 T1 T2 T3 T4 D OUTPUTLO

LOON_{for }OFF OFF ON ON HILO HI ON

_{for}OFF OFF ON ON HIHI LO ON

_{for }OFF OFF ON ON HIHI HI ON

_{rev }ON ON OFF OFF LOFigure: Circuit Diagram of a Standard 2-input TTL NAND GateCircuit Analysis:It is of interest to observe the conditions for various logic states of NAND Gate circuit, specifically with regard to estimating the power consumption in each and every state. This can be initially done by establishing the voltages at each nodes of N

_{1}– N_{7}in the circuit and then finding the net current drawn from the power supply.a)

:At Least One Input LO – Output HITo help in the analysis, the NAND Gate circuit can be re-drawn with the transistors that are non-conducting or OFF eliminated from the circuit as shown in figure below. Then the potentials, relative to ground, can be find out for each of nodes in turn. Beneath this condition, T

_{1}is ON in forward mode, T_{2}is OFF, T_{3}is OFF, whereas T_{4}is ON at the point of cut-in and thus T_{2}and T_{3}have been eliminated from the circuit.Figure: NAND Gate Circuit Redrawn with at least One Input LOA) T

_{1}ON in forward mode is operating in saturation as there is just a leakage current from T_{2}accessible as collector current, that is, T_{1}operates with a big base current and negligible collector current where I_{C MAX}= 0. The input logic LO voltage is in use as 0.1V and then:Node N

_{1}: V_{N1}= V_{i}+ V_{BE1SAT}= 0.1 + 0.8 = 0.9VB) By T

_{1}operating in saturation, its collector-emitter voltage is V_{CE SAT}= 0.1V and hence:Node N

_{2}: V_{N2 }= V_{i}+ V_{CE1SAT}= 0.1 + 0.1 = 0.2VC) With T

_{4}operating at point of cut-in its base current and therefore its collector current can be taken as zero. This signifies that there is no voltage drop across either resistor R_{1}or R_{3}and hence the potential at both sides of such resistors is equivalent to the supply voltage V_{CC}giving:Node N

_{3}, Node N_{5}: V_{N3}= V_{N5}= V_{CC}= 5VD) Node N

_{4}is pulled low by resistor R_{2}that has no current flowing via it and hence:Node N

_{4}: V_{N4}= 0VE) At last, with T

_{4}operating at the point of cut-in:Node N

_{6}: V_{N6}= V_{N3}– V_{BE4CUT-IN}= 5 – 0.6 = 4.4VAnd with the diode at cut-in as well:

Node N

_{7}: V_{N7}= V_{N6}– V_{DCUT-IN}= 4.4 – 0.4 = 4.0VThe current drawn from supply can then be obtained as:

I

_{B}= (V_{CC}– V_{N1})/R_{B}= (5 – 0.9)/4 KΩ = 1.025mAWith I

_{1}and I_{3}= 0; as negligible current flows into the collector or base of T_{4}while at the point of cut-in.Power consumption of the gate with output in the logic Hi state can then be received as:

P

_{OH}= V_{CC}x I_{B}= 5V x 1.025mA = 5.125mW:Both Inputs HI – Output LOUnder this case T

_{1}is ON in reverse mode, T_{2}is ON, T_{3}is ON and T_{4}is OFF. Figure below shows the NAND gate circuit redrawn with T_{4}eliminated. Potentials should be determined in a different order this time.Figure: NAND Gate Circuit Redrawn with Both Inputs HIWith T

_{3}ON and operating in saturation:Node N

_{4}: V_{N4}= V_{BE3SAT }= 0.8Vi) With T

_{2}too ON and in saturation:Node N

_{2}: V_{N2}= V_{N4 }+ V_{BE2SAT}= 0.8 + 0.8 = 1.6Vii) As T

_{1}is ON in reverse mode, the base-collector voltage in this mode can be taken as similar as the base-emitter voltage of a transistor operating in forward active mode and hence:Node N

_{1}: V_{N1 }= V_{N2}+ V_{BC1ONREV }= 1.6 + 0.7 = 2.3Viii) With T

_{2}operating in the saturation, its collector emitter voltage will be V_{CE SAT}= 0.1V and hence:Node N

_{3}: V_{N3}= V_{N4}+ V_{CE2SAT}= 0.8 + 0.1 = 0.9 Viv) With T

_{4}OFF no current will flow via resistor R_{3}and as a result Node N5 will be pulled up to the supply rail voltage:Node N5: V

_{N5}= V_{CC}= 5Vv) With T

_{3}ON and in the saturation, its collector-base voltage will be at a saturation value and hence the output voltage at Node N_{7}is just:Node N

_{7}: V_{N7}= V_{CE3SAT}= 0.1Vvi) With T

_{4}and diode non-conducting, the potential at Node N_{6}is rather ill-defined and depends on the resistances of the non-conducting junctions of such devices however will lie somewhere among that of Nodes N_{3}and N_{7}, that is, between 0.1 and 0.9V. Though, this voltage is not important.Current drawn from the supply, this time is given by the sum of I

_{B}and I_{1}including I_{3}= 0:Then,

I

_{B}= (V_{CC}– V_{N1})/R_{B}= (5 – 2.3V)/4 KΩ = 0.675mAAnd,

I

_{1}= (V_{CC}– V_{N3})/R_{1}= (5 – 0.9V)/1.6 KΩ = 2.56 mAThe power consumption whenever the output is LO is then as follows:

P

_{OL}= V_{CC}x (I_{B}+ I_{1}) = 5 x (0.675 + 2.56) = 16.175 mWWhen the NAND gate is supposed to spend half of its time in each and every logic state then the average power consumption can be stated as:

P

_{AVE}= (P_{OH }+ P_{OL})/2 = (5.125 + 16.175)/2 = 10.56 mWLatest technology based Electrical Engineering Online Tutoring AssistanceTutors, at the

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