The load capacitance seen by the output of inverter, in practice, is the input capacitance of loading gates and/or the capacitance of interconnecting wires as symbolized by the single load capacitance, CL, in figure below. As charge should be changed on capacitance included, current is needed to do this and time is as well needed. This signifies that the switching transients are as well affected.

Transistor Turn-Off:

Supposing the transistor to be ideal itself, then whenever the input voltage is brought to 0V, the collector current is considered to finish to flow instantly. The output voltage, though, increases exponentially as the capacitance CL, charges up to VCC via RC as shown in figure below.

Figure: Sequence of Events following Transistor Turn-Off

The following transistor turn-off, then, output voltage will follow the normal exponential growth curve and hence:

Vo(t) = VCC (1 – e-t/CLRC)

Whenever the output voltage reaches 10? of its final value at t = t10

Vo(t) = 0.1 VCC = VCC (1 – e-t10/CLRC)

Therefore,

t10 = CL RC ln (1/0.9)

Likewise, whenever the output voltage reaches 90% of its final value at t = t90 we encompass:

Vo = 0.9 VCC = VCC (1 – e-t90/CLRC)

And hence,

t90 = CL RC ln (1/o.1)

The 10% -to- 90% rise-time tR is as follows:

tR = t90 – t10 = CL RC ln (0.9/o.1)

tR = 2.2 CL RC

Usually, if RC = 1 KΩ KCL = 10pF, then tR = 22ns

It is a substantial amount of time in transistor switching terms. It should as well be remembered that in practice the capacitor charging will occur following the elimination of stored saturation charge from the base of transistor in practice. Therefore, the overall delay is the storage time, ts followed by the capacitor charging time that could reach 50ns whenever combined.

Transistor Turn-On:

The condition during turn-on of transistor is considerably distinct with capacitive loading than is the case with purely resistive loading. Transistor is another time taken to be ideal. Let consider figure below. Initially, transistor is off and the collector potential is at VCC with CL completely charged.

If the transistor is initially turned on, the charge stored by capacitor CL, can’t be eliminated instantaneously and therefore the output voltage can’t change abruptly however remains at VCC initially. However, the charged capacitor maintains a reverse bias on base-collector junction that permits the transistor to operate for a time in forward active mode.

In this mode,

iC = βF IB = βF (VCC/RB)

And a substantial portion of the collector current is supplied by capacitor, that consequently starts to discharge permitting the output voltage to decay exponentially (figure is as shown below). Ultimately, the output voltage drops to VCESAT and the transistor saturates and hence the collector current now abruptly drops to its saturation value of ICMAX ≈ VCC/RL.

Figure: Series of Events following Transistor Turn-On

By applying the Kirchhoff’s Current Law to node at collector gives:

By taking the inverse Laplace Transform:

Vo(t) = VCC e-t/CLRC + VCC (1 - σu) (1 – e-t/CLRC)

On multiplying the terms:

Vo(t) = VCC e-t/CLRC + VCC - σu VCC - VCC e-t/CLRC + σu VCC e-t/CLRC

And hence, finally in time domain:

Vo(t) = VCC - σu VCC (1 - e-t/CLRC)

This exhibits that the output voltage starts at VCC and travels towards a voltage equivalent to (1- σu) VCC, with time constant CLRC. The expression is similar to that obtained for transistor turn-on in the case of unloaded inverter however has a distinct time constant. The times at which the output voltage reaches 90% and 10% of VCC can be received in a similar way as for unloaded inverter as:

t90 = CLRC ln [σu/(σu – 0.1)] and t10 = CLRC ln [σu/(σu – 0.9)]

And hence the fall time tfCL = t10 - t90 is as follows:

tfCL = CLRC ln [(σu – 0.1)/(σu – 0.9)]

Usually, RC = 1 KΩ KCL = 10pF, σu = 5 then, tfCL = 1.8 ns

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