Setup time and hold time

Describe regarding the setup time and hold time, what will occur if there is setup time and hold tine violation and describe how to overcome this?




Set up time is the quantity of time before the clock edge which the input signal requires to be stable to guarantee it is accepted appropriately on the clock edge.

Hold time is the quantity of time after the clock edge which similar input signal has to be held before modifying it to ensure it is sensed appropriately at the clock edge.

If there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is termed as meta-stable state (quasi stable state); at the end of meta-stable state, the flip-flop settles down to either '1' or '0'. This entire process is termed as the meta-stability.

   Related Questions in Computer Engineering

2015 ┬ęTutorsGlobe All rights reserved. TutorsGlobe Rated 4.8/5 based on 34139 reviews.