A) What is body effect in CMOS circuits?
B) What does "dead zone" of a phase detector refer to?
C) What is the primary difference between linear and nonlinear oscillators?
D) What is the primary difference between a latch and a flip-flop?
QUESTION #2
Two circuits are shown in the figure above. Assume Vdd=7. The threshold voltage for NMOS transistors is 3 V and the threshold voltage for PMOS transistors is -4 V. Initially both inputs are at zero voltage. Nodes A and B are also initially at zero voltage. C is at Vdd. Similarly, nodes A' and B' are initially at zero voltage and C' is at Vdd. Both inputs have a step transition to Vdd. Determine the final voltage at nodes A, B, C, A', B', and C'. 3/15/12 ESE 324 Midterm Exam STUDENT'S NAME________________________
QUESTION #3
A relaxation based nonlinear oscillator is shown in the figure above. Note that Vdd=12 Volts and
Vss= -12 Volts.
A) Based on the resistances and capacitance, calculate the oscillation frequency at the
output.
B) What can be done to decrease the oscillation frequency?