Question) Given the command MOV BH,[4567H] and DS = 6440H, show what is on the AD0-AD7 and A8-A19 pins of an 8088 microprocessor during the execution of this command. Contents of memory are = 42H.
i. At the first clock cycle after command has been transcribed by processor.
ii. At the end of the 2nd clock cycle.
iii. During the 3rd clock cycle.
iv. Draw the timing diagram below - be sure to include the address/data bus, clock, and necessary control signals.
Question) Given the command MOV [BX],DH and DS=4000H, BX=1234H, DX=4030H, show what is on the AD0-AD7 and A8-A19 pins of the 8088 microprocessor during execution of this command.
i. At the first clock cycle after command has been transcribed by processor.
ii. At the end of the 2nd clock cycle.
iii. During the 3rd clock cycle.
iv. Draw the timing diagram below - be sure to include the address/data bus, clock, and necessary control signals.
Question) SRAM and DRAM Configurations
i. A given ROM chip has 17 address pins and 8 data pins. Find organization and the capacity.
ii. A 256K SRAM chip has 8 pins for data. Find organization and number of address pins.
iii. Show possible organizations and number of address pins for the 128K DRAM chip.
iv. Show possible organizations and number of address pins for the 256K DRAM chip.
v. Discuss the number of pins set aside for addresses in each of the following memory chips: a 64K x 4 DRAM and a 64K X 8 SRAM.
Question) Create a comparative list of the difference between SRAM and DRAM.
Question) Design a memory system to interface with the 8088 processor. The memory must have 640KB of RAM, 128KB or Video RAM, and 256KB of ROM. Show your chip selection scheme indicating what logic chips/gates you are using. You may use 512Kb SRAM chips (8 data bits) and 512Kb ROM chips (8 data bits).
Question) Design a memory system to interface with the 8086 (16-bit) processor. The memory must have 640KB of RAM, 128KB or Video RAM, and 256KB of ROM. Show your chip selection scheme indicating what logic chips/gates you are using. You may use 256Kb DRAM chips (4 data bits) and 1Mb ROM chips (8 data bits).
Question) Given 4 Bytes of hexadecimal data: 34H, 62H, 43H, and 17H.
i. Find the checksum byte.
ii. Perform checksum operation to ensure data integrity (add the 5 Bytes showing sum equal to zero).
iii. If second byte changes from 62H to 22H, show how the checksum detects the error.
iv. Explain how a parity checker would also have detected this same error.
v. If the second byte changed from 62H to 52H, would the detection of error using checksum and parity be the same? Why?