Verilog full case and parallel case

Illustrate the difference between the Verilog full case and parallel case?

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A ‘full’ case statement is a case statement in which all the possible case-expression binary patterns can be matched to case item or to a case default. When a case statement doesn’t comprise a case default and if it is possible to find out a binary case expression which doesn’t match any of the defined case items, the case statement is not ‘full’.

The ‘parallel’ case statement is a case statement in which it is just possible to match a case expression to one and just one case item. If it is possible to find out a case expression which would match more than one case item, the matching case items are termed as ‘overlapping’ case items and the case statement is not ‘parallel’.

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