--%>
Assignment Help - homework help

Use of setjmp and longjmp

Use of setjmp() and longjmp(): In C/C++, setjmp() saves the contents of the registers at a particular state in the program and longjmp() will restore that state later. In this way, longjmp() “returns” to the state of the program when setjmp() was called.

In general these functions are problematic for C++ because they do not support C++ object semantics. In particular, they do not ensure the proper destructor calls and so objects may not be cleaned up properly, leaving the system in a bad state.

Using these functions may also degrade performance by preventing optimization on local variables. For C++ exception handling, try/catch constructs are recommended instead.

214_serjmp.jpg

For model checking in particular, non-hierarchical long jumps are difficult to model with modeling languages like Java. These functions need to do register restoration which requires modeling of registers and their related operations, adding considerable overhead to model-checking effort.

   Related Questions in Programming Languages

  • Q : Functions of states of the

    Mention the different states of the XMLHttpRequest an dalso describe their functions.

    		•
  • Q : Describe Timers Timers: While time

    Timers: While time values usually cannot be reduced in the target system, their usage can be encapsulated as an abstraction which can be replaced easily (e.g., by a non-deterministic choice) during model checking.

  • Q : Installation of Symbian SIS file to

    I am not capable to install Symbian SIS file to Symbian OS v.9.x tool? What must I do?

    		•
  • Q : Write a recursive implementation of

    Assignment 5 Selecting Array Elements Implement the following C++ code in assembly language, using the block-structured .IF and .WHILE directives. Assume that all variables are 32-bit signed integers: int array[] = {10,60,20,33,72,89,45,65,72,18}; int sample = 50; intArraySize = s

    		•
  • Q : State the term VHDL or Verilog State

    State the term VHDL or Verilog? Answer: VHDL is extremely high speep integrated chips hardware descripted language as well as verilog is use to verify logic.

    		•
  • Q : What is Static initializer Static

    Static initializer: An initializer prefixed with ‘static’ reserved word. The static initializer is stated outside the methods of its enclosing class, and might access only the static fields and methods of its enclosing class.

    		•
  • Q : What is single user sysytem What is

    What is meant by the single users system?

    		•
  • Q : Use the Processing program for the

    1. Here is a short program. It prints out the value of a variable "x". Ernie and Bert disagree about what will be printed: Ernie says, the value gets changed in "changeX" so it will print "7", and Bert says, no, when the function exits the changes get reversed and the value goes back to "5". Expl

    		•
  • Q : Type promotion rule Q. Explain type

    Q. Explain type conversion rules for basic data types in java. Ans. Type promotion rule: Java automatically each bits or short operant to int when evaluating an expression. As usual as the automatic promotion

    		•
  • Q : Explain Exclusive-or operator

    Exclusive-or operator: An exclusive-or operator (^) is both a Boolean operator and the bit manipulation operator. The Boolean version provides the value true when only one of its operands is true; or else it offers the value false. Likewise, the bit m

    		•