Usage of the Verilog function

Illustrate the rules governing the usage of the Verilog function?




The given rules govern the usage of the Verilog function construct:

a) The function can’t advance simulation-time, by using constructs such as #, @ and so on.

b) The function shall not encompass non-blocking assignments.

c) The function devoid of a range defaults to a one bit reg for return value.

d) This is illegal to declare the other object with similar name as the function in the scope where function is declared.

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