Module instantiation concepts

What happens to logic after synthesis, which is driving an unconnected output port which is left open (that is, no connect) throughout its module instantiation?

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The unconnected output port in simulation will drive a value; however this value doesn’t propagate to any other logic. In synthesis, the cone of any combinatorial logic which drives the unconnected output will get optimized away throughout the boundary optimization, that is, optimization through synthesis tools across the hierarchical boundaries.

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