Clock skew to zero

Is it possible to decrease the clock skew to zero? Describe your answer?




Even although there are clock layout strategies (H-tree) which can in theory decrease the clock skew to zero by having the similar path length from each and every flip-flop from the pll, process variations in the R and C across the chip will cause clock skew and also a pure H-Tree scheme is not practical (uses too much area).

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