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consider a conventional npn bjt with uniform doping the base-emitter junction is forward biased and the base-collector
assume that the gate oxide between an n poly-si gate and the p-substrate is ii a thick and na lei8 cm3a what is the vi
an nmosfet with a threshold voltage of 05 v and oxide thickness of 6 nm has a v dsat of 075 v when biased at vg 25 v
p-channel mosfet with heavily doped p-type poly-si gate has a threshold voltage of -i s y with v sb 0 v when a 5 v
answer the following questionsa in an older mosfet technology the field oxide is a 1 m thick thennal oxide would you
answer each of the following questions in one to three sentencesa what is lithography fieldb what is misalignment in
for the following process steps assume that you use a positive photoresist and that etch selectivity is infinite a
applying the depletion approximation to a linearly graded junction withderive expressions rora the electric field
a for an electron mobility of 500 cm2nmiddots calculate the time between collisions ta ke mil moin these calculationsb
a metan-type semiconductor schottky diode has the cv characteristic given in fig 4-54iii what is the built-in voltage
cv and id - vg characteristics of a hypothetical mosfet with channel length l i microm are given in fig 6-40a is the
metal interconnect lines in ie circuits form parasitic mos capacitors as illustrated in fig 5-37 generally one wants to
consider the c-v curve of an mos capacitor in fig 5-38 the solid line the capacitor area is 6400 microm2 c0 45 pf and
answer the following questions based on the c-v curve for an mos capacitor shown in fig 5--39 the area of the capacitor
from the high-frequency c- v measurements on an mos capacitor with p-si substrate performed at 300 k the following
a qualitatively describe the differences among sram dram and flash memory in terms of closeness to the basic cmos
asswne the field oxide between an n poly-si wire and the p-substrate is 03 jlm thick and that na 5el7 cm-3a what is
a what is the advantage of having a small wdepb for given land vt what is the impact of reducing wdep on 1ds1t and gate
the voltage transfer curve of an inverter is given in fig 6--46 the threshold volt ages of the nfet and pfet are -04
a determine the flat-band voltage of the nmos and pmos capacitors f3bricated on the same chip the devices are shown in
consider an npn transistor with we 05 11m we 02 11m we 2 11m da 10 cm2sa rnd the peak szligf from fig 8-27 v bil vb
the emitter of a high-pfsrr should be heavily dopeda is it desirable to replace the emitter in bjt with a metalb
an npn bjt is biased so that its operating point lies at the boundary between active mode and saturation modea
a step change in base current occurs as shown in fig 8- 29 assuming forward active operation estimate the collector